NEURAL NETWORK PROCESSING ASSIST INSTRUCTION

Patent №

US 11,669,331

Granted

2023-06-06

Filed 2021

Owner

INTERNATIONAL BUSINESS MACHINES CORPORATION

Lab

IBM Research

AI components

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

17350393

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A first processor processes an instruction configured to perform a plurality of functions. The plurality of functions includes one or more functions to operate on one or more tensors. A determination is made of a function of the plurality of functions to be performed. The first processor provides to a second processor information related to the function. The second processor is to perform the function. The first processor and the second processor share memory providing memory coherence.

AI hardwareG06F 9/3838G06F 9/30014G06F 9/30036G06F 9/30076G06F 9/3877G06F 9/3887G06F 9/544G06N 3/02+1 more

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AI classification

AI hardware1.00

Speech0.00

Evolutionary computation0.00

Natural language0.00

Knowledge representation0.00

Machine learning0.00

Planning0.00

Vision0.00

Ownership

INTERNATIONAL BUSINESS MACHINES CORPORATION

assignment · 565790060

Assignors

ALBARAKAT, LAITH M., BRADBURY, JONATHAN D., SLEGEL, TIMOTHY, LICHTENAU, CEDRIC, WEISHAUPT, SIMON, SAPORITO, ANTHONY

On an employer assignment, the assignors are typically the inventors.

From the same owner

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Cites (33)

SPARSE CONVOLUTIONAL NEURAL NETWORK ACCELERATORUS 10,891,538 · 2021 On-Device Neural Networks for Natural Language UnderstandingUS 10,885,277 · 2021 MERGING MULTIPLE NODAL NETWORKSUS 10,832,137 · 2020 NEURAL NETWORK ACCELERATION AND EMBEDDING COMPRESSION SYSTEMS AND METHODS WITH ACTIVATION SPARSIFICATIONUS 10,832,139 · 2020 DEVICE FOR IMPLEMENTING ARTIFICIAL NEURAL NETWORK WITH FLEXIBLE BUFFER POOL STRUCTUREUS 10,824,939 · 2020 POWER SAVINGS FOR NEURAL NETWORK ARCHITECTURE WITH ZERO ACTIVATIONS DURING INFERENCEUS 10,817,042 · 2020 HARDWARE ACCELERATOR FOR COMPRESSED GRU ON FPGAUS 10,810,484 · 2020 COMBINING CPU AND SPECIAL ACCELERATOR FOR IMPLEMENTING AN ARTIFICIAL NEURAL NETWORKUS 10,802,992 · 2020 COMPILER AND HARDWARE ABSTRACTION LAYER ARCHITECTURE FOR A NEURAL NETWORK ACCELERATORUS 10,789,402 · 2020 OUTLIER DETECTION FOR STREAMING DATA USING LOCALITY SENSITIVE HASHINGUS 10,778,707 · 2020 METHOD AND APPARATUS FOR DESIGNING AND IMPLEMENTING A CONVOLUTION NEURAL NET ACCELERATORUS 10,726,328 · 2020 DATA STRUCTURE DESCRIPTORS FOR DEEP LEARNING ACCELERATIONUS 10,726,329 · 2020 INSTANCE UPGRADE MIGRATIONUS 10,728,169 · 2020 CLUSTER OF SCALAR ENGINES TO ACCELERATE INTERSECTION IN LEAF NODEUS 10,699,465 · 2020 SPILLING TEMPORARY RESULTS FOR ACCOMMODATION OF MEMORY BOUNDARIESUS 10,673,460 · 2020 ENHANCED LOW PRECISION BINARY FLOATING-POINT FORMATTINGUS 10,656,913 · 2020 SYSTEM AND METHOD FOR INCREASING ACCURACY OF APPROXIMATING QUERY RESULTS USING NEURAL NETWORKSUS 10,642,835 · 2020 GENERAL-PURPOSE PROCESSOR INSTRUCTION TO PERFORM COMPRESSION/DECOMPRESSION OPERATIONSUS 10,630,312 · 2020 MATRIX MULTIPLICATION ACCELERATION OF SPARSE MATRICES USING COLUMN FOLDING AND SQUEEZINGUS 10,620,951 · 2020 METHOD AND APPARATUS FOR LOADING A MATRIX INTO AN ACCELERATORUS 10,558,599 · 2020 SYSTEM AND METHOD FOR BINARY THROTTLING FOR LIVE MIGRATION OF VIRTUAL MACHINESUS 10,552,199 · 2020 REDUCING COMPUTATIONS IN A NEURAL NETWORKUS 10,460,230 · 2019 NEURAL NETWORK UNIT WITH SHARED ACTIVATION FUNCTION UNITSUS 10,387,366 · 2019 TININESS PREDICTION AND HANDLER ENGINE FOR SMOOTH HANDLING OF NUMERIC UNDERFLOWUS 10,379,814 · 2019 DATA PROCESSING ARCHITECTURE FOR IMPROVED DATA FLOWUS 10,346,198 · 2019

and 8 more

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