SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device has a NOR-type memory cell array, a crossbar array, an entry gate, and a column selecting/signal processing unit. The crossbar array has a plurality of rows and columns, variable resistor elements formed in intersections of rows and columns respectively. The entry gate arranged between the memory cell array and the crossbar array, connects a selected bit line of the memory cell array to the crossbar array based on a selection signal. The column selecting/signal processing unit has a column writing unit, a column reading unit, and a NOR writing unit. The column writing unit writes data read from the memory cell array to a selected column of the crossbar array. The column reading unit reads data of the selected column of the crossbar array. The NOR writing unit at least writes data read by the column writing unit to the memory cell array.