MEMORY DEVICE WITH IN-MEMORY COMPUTING ARCHITECTURE AND COMPUTING METHOD THEREOF

A memory device and a computing method are provided. The memory device includes a memory array, comprising a first and second memory blocks, and a comparator. The first memory block performs a multiplication and accumulation (MAC) operation according to a first weight matrix and a first input matrix to generate a first sum. The second memory block performs the MAC operation according to a second weight matrix and a second input matrix to generate a second sum. The comparator compares the first and second sums. In a first configuration, each value of the input and second input matrixes are the same and each value of the first and second weight matrixes are complements. In a second configuration, each value of the first and second input matrixes are complements and each value of the first and second weight matrixes are the same.