Patent US 4,064,533

A CCD focal plane processor having a plurality of columns of individual sensor elements with plural sensor elements per column. The structure includes plural CCD shift registers corresponding to the number of columns of sensors, each CCD shift register including a pair of stages corresponding to each of the element sensors of the corresponding column of the array. Two "snapshots" of the scene are taken at time-displaced intervals and are compared to detect differences therebetween to eliminate background, or unchanging scene content. The individual sensors provide outputs which are injected into the .alpha. stages of the corresponding paired shift register stages of each CCD shift register in a first time interval corresponding to the first "snapshot". The resulting charge packets in the first (.alpha.) stages then are advanced to the second (.beta.) stages of each shift register pair. The second "snapshot" corresponds to injecting a second signal into the .alpha. stages of the plurality of pairs of .alpha., .beta. stages. The CCD shift registers then are read out simultaneously and in succession as to the plural, related .alpha., .beta. pairs of stages containing the time-displaced elemental signal samples. A further CCD shift register including a number of .alpha., .beta. pairs of stages receives the parallel .alpha., .beta. outputs in corresponding time sequential manner to maintain the .alpha., .beta. related pair arrangement of the time-displaced elemental samples. An output circuit compares the .alpha., .beta. signals for each elemental area and determines the difference therebetween. A CRT display receives the difference signal outputs for displaying moving target information.