HIGH RESOLUTION IMAGER EMPLOYING STAGGERED SENSOR STRUCTURE

A high density charge coupled device imaging array 58 with a bilinear array 60, 62 of photosites on a single integrated circuit chip is utilized in an image scanning configuration. Offset photosites 60a, 62a in two rows are coupled via transfer gates 64 to storage register 72 and then to two shift registers 74, 76, and via transfer gates 66 directly to two shift registers 68, 70 in a quadrilinear array. The output of these four shift registers 68, 70, 74, 76 are multiplexed to generate a single output pulse train representative of the information scanned.