Patent US 4,130,879

A scientific processing unit includes apparatus for performing floating point multiplication operations with operands in binary coded form. The apparatus is constructed from standard multibit LSI microprocessor chips organized into a number of vertical slices. Each chip includes an arithmetic logic unit (ALU) and a random access memory (RAM). The ALU's are used to generate a predetermined number of submultiples of a mantissa portion of a floating point number which are stored in the chips memories. The submultiples are generated by multiplying the mantissa by predetermined factors which correspond to the values of multiplier digit positions selected during the multiplication operation. The apparatus further includes selection circuits which provide for selection of the least significant bit positions from each of a number of groups of multiplier digits during the multiplication operation. The least significant bit positions selected are used to read out the entire submultiple from the chip memories which thereafter are summed to produce a final product.