Patent US 4,173,041

A microcontrol extension mechanism for increasing the number of control actions for a processor data flow section in the same manner as could be accomplished by increasing the length of the microwords in the processor control store but without actually increasing the length of such microwords. The additional control actions are obtained by means of a relatively small read only storage array having stored therein a separate pluralbit mode word for each of the different machine macroinstruction operation codes. This read only storage array is directly addressed by the operation code of the macroinstruction being processed to cause a read out of its corresponding mode word, which mode word is then set into a mode register. The output lines of the mode register are coupled to the desired additional control points in the processor data flow section. A second small read only storage array is also provided for storing the starting addresses for the different operation code microroutines in the processor control store. During the fetching of the macroinstruction to be processed, the operation code portion of such macroinstruction is used to address this second read only storage array to cause it to supply to the address register for the control store the starting address for the sequence of microwords to be used in executing such macroinstruction.