Patent US 4,183,459

An automatic test apparatus coupled to a bit-directional internal data and control bus of a programmed microprocessor-based system tests the performance of the system in real time. Signal responses of the bus within a known good system are compared in real time to signal responses on the bus of an unknown system in order to identify faults. Faults are isolated by a sequential algorithm which stops operation at the occurrence of the first fault and thereupon traces the error to the subsystem or components supplying the indicated error signal to the bi-directional bus.