Patent US 4,622,669

A test module is provided for troubleshooting and diagnosing hardware failures in the interface logic to an asynchronous microprocessor bus at true operating speed until a fault occurs. If a fault is detected, the circuit will halt a microprocessor under test coupled to the asynchronous microprocessor bus and freeze the state of the bus signal lines. The microprocessor under test has bit pattern sets therein. A test microprocessor has test pattern sets stored in internal memory. Test pattern latches are coupled to the test microprocessor for sequentially latching the test pattern sets. Address bus latches and data bus latchs are coupled to the asynchronous bus for latching the state of the address lines as a pattern under test. A comparator is coupled to the asynchronous bus, the test microprocessor, the first means, and the second means, for comparing one of the bit patterns to one of the test patterns wherein a continue signal is supplied to the asynchronous bus and the test microprocessor when the test pattern and the bit pattern are the same so that another of the test patterns and another of the bit patterns may be compared. A diagnose signal is supplied to the test microprocessor when the test pattern and the bit pattern are not the same. Fault latches are coupled to the address bus latches and data bus latches, the test microprocessor, and the asynchronous bus, for outputting the bit pattern when the diagnose signal is generated.