CHIP TOPOGRAPHY FOR MOS PACKET NETWORK INTERFACE CIRCUIT

An optimum chip topography for a MOS LSI packet network interface circuit, including electrical interface and input/output circuitry disposed around the periphery of said chip and forming approximately a quadrilateral framework surrounding the remainder of the circuitry; a read only memory (ROM) disposed in one corner of the interface framework; a microcontroller disposed adjacent to the ROM and along part of a first side of the interface framework; direct memory access (DMA) circuitry disposed adjacent to the microcontroller and in a second corner of the interface framework; transmitter circuitry disposed adjacent to the DMA and microcontroller circuitry and along part of a second side of the interface framework; receiver circuitry disposed adjacent to the transmitter circuitry and in a third corner of the interface framework; data access line circuitry comprising part of a third side of the interface framework, and situated adjacent to the receiver circuitry; timing/counting circuitry disposed adjacent to the receiver circuitry and the data access line circuitry and in the fourth corner of the interface framework; read/write control circuitry comprising part of the fourth side of the interface framework, and situated adjacent to a portion of the receiver circuitry; input/output register circuitry disposed within the interior of the chip and adjacent to the timing/counting circuitry, the read/write control circuitry, the microcontroller, and the ROM; and internal register circuitry disposed within the interior of the chip and adjacent to the input/output register circuitry, the ROM, and the microcontroller. The invention further provides a novel indirect data addressing method and a data buffer allocation method for optimizing the use of the memory and processing resources of a host processor.