AMBIGUOUS VIRTUAL CHANNELS

Patent №

US 7,269,695

Granted

2007-09-11

Filed 2006

Owner

—

Lab

—

AI components

kr · hardware

Assignment

None on record

Dataset

AIPD

2023_r1 edition

Application

11514119

An apparatus comprises a first plurality of buffers configured to store operations belonging to a first virtual channel and a control circuit coupled to the first plurality of buffers. The first virtual channel includes first operations and second operations, wherein each of the first operations depend on at least one of the second operations during use. A first number of the first operations is less than or equal to a maximum. It is ambiguous, for a first received operation in the first virtual channel, whether the first received operation is one of the first operations or the second operations. A total number of the first plurality of buffers exceeds the maximum.

Knowledge representation AI hardwareG06F 12/0831

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AI hardware0.96

Knowledge representation0.94

Machine learning0.21

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Natural language0.11

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Cites (24)

AMBIGUOUS VIRTUAL CHANNELSUS 7,114,043 · 2006 SYSTEM HAVING INTERFACES AND SWITCH THAT SEPARATES COHERENT AND PACKET TRAFFICUS 6,941,406 · 2005 SYSTEM HAVING INTERFACES AND SWITCH THAT SEPARATES COHERENT AND PACKET TRAFFICUS 6,748,479 · 2004 STORE BUFFER WHICH FORWARDS DATA BASED ON INDEX AND OPTIONAL WAY MATCHUS 6,662,280 · 2003 SOURCE CONTROLLED CACHE ALLOCATIONUS 6,574,708 · 2003 METHOD, SYSTEM, AND PROGRAM FOR MANAGING REQUESTS TO A CACHE USING FLAGS TO QUEUE AND DEQUEUE DATA IN A BUFFERUS 6,438,651 · 2002 USER-PRIORITIZED CACHE REPLACEMENTUS 6,349,365 · 2002 ALLOCATION FOR BACK-TO BACK MISSES IN A DIRECTORY BASED CACHEUS 6,332,179 · 2001 MEMORY ARBITRATION SCHEME WITH CIRCULAR SEQUENCE REGISTERUS 6,321,309 · 2001 APPARATUS AND METHOD FOR CONFIGURABLE USE OF GROUPS OF PADS OF A SYSTEM ON CHIPUS 6,262,594 · 2001 DISTRIBUTED PIPELINE MEMORY ARCHITECTURE FOR A COMPUTER SYSTEMUS 6,209,020 · 2001 PROCESSOR-CACHE PROTOCOL USING SIMPLE COMMANDS TO IMPLEMENT A RANGE OF CACHE CONFIGURATIONSUS 6,202,125 · 2001 SHARED CACHE STRUCTURE FOR TEMPORAL AND NON-TEMPORAL INFORMATION USING INDICATIVE BITSUS 6,202,129 · 2001 DATA TRANSACTION TYPING FOR IMPROVED CACHING AND PREFETCHING CHARACTERISTICSUS 6,151,662 · 2000 PREFETCHING AND CACHING DOCUMENTS ACCORDING TO PROBABILITYRANKED NEEDS LISTUS 6,098,064 · 2000 FAIR DATA BUS ARBITRATION SYSTEM WHICH ASSIGNS ADJUSTABLE PRIORITY VALUES TO COMPETING SOURCESUS 6,092,137 · 2000 HIGH PERFORMANCE SHARED MEMORY FOR A BRIDGE ROUTER SUPPORTING CACHE COHERENCYUS 6,018,763 · 2000 EFFICIENT ALLOCATION OF CACHE MEMORY SPACE IN A COMPUTER SYSTEMUS 5,893,150 · 1999 SINGLE CHIP NETWORK ADAPTER APPARATUSUS 5,887,187 · 1999 COMPUTER SYSTEM AND METHOD OF ALLOCATING CACHE MEMORIES IN A MULTILEVEL CACHE HIERARCHY UTILIZING A LOCALITY HINT WITHIN AN INSTRUCTIONUS 5,829,025 · 1998 CHIP TOPOGRAPHY FOR MOS PACKET NETWORK INTERFACE CIRCUITUS 4,433,378 · 1984 Patent US 4,463,424US 4,463,424 Patent US 5,640,399US 5,640,399 Patent US 6,021,451US 6,021,451

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