A MOS TRANSISTOR TYPE INTEGRATED CIRCUIT FOR THE EXECUTION OF LOGICAL OPERATIONS ON A PLURALITY OF DATA SIGNALS

Four-pole circuits for iterative modular use in integrated circuits fabricated with complementary MOS (C-MOS) technology or LOCMOS technology, having a high density of circuit elements and high speed obtained at low dissipation. Each of said four-pole circuit modules has two signal inputs, a control input and a signal output line. The four-pole circuit modules may be constructed from two series connected complementary MOS transistors or two series-connected p-MOS transistors. In the latter case the control input must be doubled to receive the control signal and its inverted value. The signal outut is then alternatively connected to one of the two signal inputs (logically or physically) by each of the two values of the control signal. This two-level logic, input signal and control signal, results in circuit modules easily used in computer aided design for multiplexers in which said four-pole circuits are successively arranged in two or more levels, for a BUS-configuration; and can be arranged in series having a common control and different combinations of input signals to form an arithmetic member for one bit in respect of two input quantities. Series of this kind can be combined to form a multi-bit arithmetic member.