CACHE MEMORY USING A LOWEST PRIORITY REPLACEMENT CIRCUIT

A data processing system having a processor, main memory, and a cache memory system which implements the least recently used replacement algorithm in replacing cache memory words with main memory words. The cache memory system is comprised of a cache control circuit and a plurality of cache memories. Each cache memory stores cache memory words having a similar time usage history. The first cache memmory stores cache memory words which are more recently used than the cache memory words in the second cache memory, and the second cache memory stores cache memory words which are more recently used than the cache memory words in the third cache memory. When a main memory word must be transferred to the cache memory, the main memory word is stored in the first memory; and the first cache memory's least recently used cache memory word is stored in the second cache memory. The least recently used cache memory word from the second cache memory is stored in the third cache memory. These operations maintain the proper time usage history of the cache memories.