A MEMORY SYSTEM WITH WRITE BUFFER, PREFETCH AND INTERNAL CACHES

A statistically fast, high performance computer memory system including a system memory for storing code and non-code data accessible by at least two bus masters, a bus connecting the memory with the bus masters, and a plurality of caches connected to the bus. An internal cache holds data selected solely on the basis of memory accesses by the host processor, a pre-fetch cache pre-fetches code from the memory, and a write buffer cache connected to the bus for buffering data written to the memory.