MULTIPLE PROCESSING CELL DIGITAL DATA PROCESSOR

The invention provides a digital data processor which has been systemetized down to bit level. The processor includes a regular array of identical processing cells which perform a logic operation on incoming bits. The cells repeatedly perform a cell operation under the control of clocks which govern the inputting to and outputting from the cell of data bits. Each bit takes part in a maximum of one cell operation in one repetition of the clock having the highest repetition frequency. Processing cell arrays for dealing with larger numbers may be readily built up from smaller arrays used for smaller numbers. Having obtained a fully working design for one type of processing cell, the full array consisting of a plurality of cells is proven.