ASSOCIATIVE ARRAY WITH FIVE ARITHMETIC PATHS

An associative processor array including M rows and N columns of identical processing cells with each cell connected horizontally to its left and right to a neighboring cell. Each cell includes a memory for storing control and data information with the output of the memory coupled to an arithmetic logic unit (ALU) and with the output of the ALU coupled to register means associated with each cell. The entire array formed by the individual cells is capable of performing arithmetic operations on digital words where each word consists of a plurality of bits and a given number of slices. Pursuant to this invention the cells are coupled together in a row via five data paths wherein a first path is operative to move a bit from left to right or from right to left and which first data path is coupled to the memory means in the cells. The second data path is coupled to the ALU's and operative to propagate the arithmetic carry from the ALU of any of the cells unidirectionally to another cell in the same row. A third data path is coupled to each of the cells in the row and operates to move a second bit from one cell to the next in a given selected direction. There are means associated with each cell responsive to the second bit to store the same. The fourth data path is coupled to each of the cells in the row and operative to move a third bit from the ALU of one cell to the next cell, and a fifth data path is operative to move a fourth bit bidirectionally and includes storage register means for storing said fourth bit to enable said cell to operate to perform said arithmetic function according to the bit as stored in the cell.