LATCHING CIRCUIT SPEED-UP TECHNIQUE

A latching circuit with reduced signal delay is disclosed comprising a latch and an output logic function circuit. The same signals are applied to the output gate of the latch and to the logic function circuit, whereby the output gate and the logic function circuit effectively are connected in parallel, rather than in series, to eliminate one level of logic delay. An additional logic signal is applied only to the logic function circuit but not to the latch. Provision can be made for applying inverted data to the latch in the event that the latch and the logic function circuit are implemented with NAND or NOR gates.