SYSTEM FOR TESTING DIGITAL LOGIC DEVICES

A functional testing system for programmable logic devices. Test vectors are generated by a shift register and applied to the contact pins of the logic device through isolation elements so that all pins may be treated alike regardless of whether they are inputs or outputs. The logic level on pins that are outputs are controlled by the logic device, while logic levels on pins that are inputs are controlled by the shift register. The response of the logic device to the test vector is recorded in an output shift register and the response is then shifted out of the shift register to one input of an exclusive OR gate that also receives outputs from predetermined stages of the test vector shift register to create a pseudo-random function. The output of the exclusive OR gate is shifted into the test vector shift register as each bit of the logic device's response is applied to the exclusive OR gate thereby creating a new test vector. The number of test vectors applied to the logic device is counted and when a predetermined number is reached, the test terminates and the current test vector is then stored and compared to the final test vector obtained by performing the same test on an identical circuit known to be operating correctly. The testing system thus evaluates the functionality of the logic device while also providing the stimulus to the device.