METHOD AND APPARATUS FOR CONVERTING A PROGRAMMABLE LOGIC DEVICE DESIGNED INTO A SELECTABLE TARGET GATE ARRAY DESIGN

The present invention is a translation system that translates a definition of a prototyped programmable device defined in a programmable device specification into a generic behavioral model of the device and into lists of logic blocks and connections for implementing the device as a non-programmable device in an application specific target technology. The lists and behavioral models are used to create command files that drive logic synthesis and network connection list processing operations to generate a generic list of logic and network connections. The generic list and commands are used to create device test vectors for testing the behavior of the model and the target device design. The target technology lists and command files are processed to reduce redundant logic and are mapped into logic blocks and connection lists in the target technology. The operation of the target technology design is simulated using the target logic blocks and connections and the test vectors. The behavioral model is compiled to allow behavioral simulation of the operation of the device using the same test vectors. When the simulation of the target technology and the behavioral model produce identical outputs, the target non-programmable design exactly matches the operation of the prototype programmable device and the target technology design can then be used in mass production of the logic device.