NON-VOLATILE MEMORY CIRCUIT HAVING A COMMON WRITE AND ERASE TERMINAL

A non-volatile memory circuit comprising a plurality of semiconductor non-volatile memory elements, with erasure of data stored in all of these elements, enabling of selective write-in to all of the elements and read-out of stored data being controlled by potentials applied to a single control terminal. Use of a single terminal for these functions, rather than a pair of terminals as in the prior art, makes the circuit highly suitable for ultra-miniature electronic device applications.