OVERFLOW DETECTOR FOR ALGEBRAIC ADDERS

An MOS high-speed overflow detector for algebraic adders which add two binary numbers (a,b) in two's complement notation and contain one full adder per digit which provides a sum signal (s) and a carry signal (c) consists of a complex gate (k) made up of three two-input AND elements (u1, u2, u3). The outputs of the three AND elements are NORed. The two inputs of the first AND element (u1) are fed with the sign signal (va) of the first binary number (a) and with the inverted sign signal (vb) of the second binary number (b), respectively. The two inputs of the second AND element (U2) are fed with the sign signal (vb) of the second binary number (b) and with the sum signal (vs) of the full adder (av) of the sign digit, respectively. The two inputs of the third AND element (u3) are fed with the inverted sum signal (vs) and the inverted sign signal (va) of the first binary number (a), respectively.