Patent №
US 4,592,007
Granted
1986-05-27
Filed 1982
Owner
TOKYO SHIBAURA DENKI KABUSHIKI KAISHA, A CORP.OF JAPAN
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
06428033
The invention provides a full adder having a logic circuit which has an inverter and a selector circuit, a logic circuit which has an inverter and a selector circuit, and a logic circuit which has a selector circuit and an inverter so as to produce a sum output signal S and a carry output signal C in response to three input signals X, Y and Z.
AI hardwareG06F 7/5016
AI classification
AI hardware0.99
Vision0.11
Evolutionary computation0.00
Natural language0.00
Speech0.00
Machine learning0.00
Knowledge representation0.00
Planning0.00
Ownership
TOKYO SHIBAURA DENKI KABUSHIKI KAISHA, A CORP.OF JAPAN
assignment · 40520157
Assignors
OHHASHI, MASAHIDE
On an employer assignment, the assignors are typically the inventors.
From the same owner
CONTINUOUS SPEECH RECOGNITION APPARATUSUS 4,677,673 · 1987SPEECH SYNTHESIZING APPARATUSUS 4,669,121 · 1987PATTERN RECOGNITION APPARATUS AND METHOD FOR MAKING SAMEUS 4,651,289 · 1987DIGITAL SUPERIMPOSED EDGE GENERATION APPARATUSUS 4,646,154 · 1987PROFILE MEASUREMENT APPARATUS USING RADIATIONUS 4,633,420 · 1986ARITHMETIC CONTROL APPARATUS FOR A PIPELINE PROCESSING SYSTEMUS 4,631,672 · 1986TRACKING INPUT DEVICEUS 4,626,908 · 1986MONOSYLLABLE RECOGNITION APPARATUSUS 4,625,287 · 1986