IMAGE PROCESSOR

This invention provides parallel partial image processing such as spatial convolution or non-linear neighbor arithmetic operation using an image processor which can easily be formed as a large-scale integrated circuit and can be used for various purposes. The image processor has an adder-subtractor, a multiplier, a reciprocal number memory in which the reciprocal of an address and the amount of shift are stored at each address, and a shift register. The processor therefore is capable of high-speed dividing operations by multiplying a multiplicant by the reciprocal of a multiplier and by shifting the result of the multiplication. Also, by switching the inputs to the adder-subtractor and to the multiplier rapidly under program control, it is possible to perform arbitrary addition, subtraction, multiplication and division on partial image data of m rows and n columns stored in a partial image memory of the image processor.