DIRECT WRITE NONVOLATILE MEMORY CELLS

A floating gate type nonvolatile memory cell of the general class known as electrically erasable programmable read only memories, configured with a single polysilicon layer, operable in a direct write mode, and characterized by its absence of read disturb. In one form of its practice, the floating gate is divided into three regions situated with relation to specified regions in the substrate. The first region of the floating gate is dielectrically isolated from a conductively doped region in the substrate so as to form a capacitor; the second region is similarly situated, but forms a significantly smaller capacitor and utilizes a dielectric suitable for Fowler-Nordheim tunneling or Poole-Frenkel conduction of charge therethrough; and the third region overlaps a channel of a field effect type sense transistor, conduction through which is responsive to the charge resident on the floating gate. Access to the substrate regions is by way of three electrically independent but simultaneously enabled access transistors. Writing of data is accomplished by the division of voltage between capacitors, while reading is accomplished by detecting the conductive state of the sense transistor in an electrically independent conductive path.