PARALLEL PROCESSING SYSTEM APPARATUS

Configured for accelerated operation of processing elements in a SIMD parallel processing system is disclosed. The output of an exclusive-OR gate is coupled to one input of the element ALU while a first input of the gate is adapted to receive signals intended for the ALU input. Upon loading a `1` bit into a register coupled to a gate second input, signals applied to the gate first input are complemented and applied to the ALU input. As a result, different arithmetic and logic operations can be performed simultaneously by different elements in the processing system in response to a single series of instructions.