MICROCODE COMPUTER HAVING DISPATCH AND MAIN CONTROL STORES FOR STORING THE FIRST AND THE REMAINING MICROINSTRUCTIONS OF MACHINE INSTRUCTIONS

A computer includes a memory for storing the machine instructions therein and an arithmetic logic unit for carrying out logical and arithmetic operations. An instruction processing unit is provided for receiving and decoding machine instructions which are received from the memory. The instruction processing unit produces an entry address for the first microinstruction which corresponds to the machine instruction which was decoded by the instruction processing unit. A dispatch control store is connected to receive the entry address and further has stored therein the first microinstruction for each of the machine instructions. The dispatch control store produces a selected one of the microinstructions stored therein upon receipt of the entry address. A main control store is provided for storing therein all of the microinstructions for each of the machine instructions other than the first microinstruction for each of the machine instructions. Circuitry is provided for conveying the entry microinstruction corresponding to the entry address from the dispatch control store to the arithmetic logic unit and subsequently for conveying sequentially the remainder of the microinstructions from the control store to the arithmetic logic unit for decoded machine instruction.