FIELD PROGRAMMABLE MATRIX CIRCUIT FOR EEPROM LOGIC CELLS

An improved field programmable matrix circuit. The matrix circuit includes a plurality of pairs of input lines having noninverted and inverted inputs. These input lines intersect a plurality of output column lines. A single transistor is used to provide a programmable connection to each column line from both the inverted and noninverted inputs of an input line pair. The transistor has a source, a drain and a gate with either the source or the drain coupled to a voltage potential and the other of the source or the drain coupled to an output column line. The gate is alternately coupled to a noninverted input, an inverted output, or a second voltage potential. The second voltage potential is coupled when it is desired to hold the transistor in an off state.