Patent US 4,495,590

In this programmable logic array (PLA), internal array lines are shared by several sets of input array lines. Each set of input lines operates on a separate time phase. This PLA construction is denser than some other arrangements of multiple PLAs, and some of its components are reduced in number as compared with multiple independent PLAs for the same functions. A new pipelined multiplier is disclosed as one application for the PLA of this invention. In another application for this PLA, the array lines are shared where the array locations that are otherwise required for don't care states have been eliminated and a denser construction is provided.