SIGNAL PROCESSING INTEGRATED CIRCUIT FOR ROW AND COLUMN ADDITION OF OF MATRICES OF DIGITAL VALUES

A signal-processing circuit performs a cosine type transformation (double addition in rows and columns) of values of a matrix of n rows and n columns. An architecture is proposed with a row transform circuit, a column transform circuit and a buffer memory of nxn words. The memory is addressed sequentially, line by line, during the storage of nxn coefficients C.sup.i (v) which are the results of the row transform on a block of nxn data. Then it is addressed sequentially, column by column, during the storage of nxn coefficients C.sup.i (v) corresponding to the processing of the following block. At each address, a read stage of a coefficient is performed followed by the writing of a new coefficient. The invention can be applied to circuits for the digital processing of images to prepare the compression of data before transmission.