Patent US 4,875,212

A semiconductor memory device, comprising an information memory array storing data words each consisting of a predetermined number of information bits, a memory array storing bits generated in accordance with an error detect/correct code, the memory array having bit lines equal in number to the information bits forming each of the data words, the memory array being programmable to create error detection and correction data on the basis of which a bit in error in the main memory array is to be detected and corrected, main sense amplifiers for detecting the information bits read from the main memory array, the main sense amplifiers being equal in number to the information bits forming each of the data words, auxiliary sense amplifiers for detecting an error bit read from the main memory array and output through the main sense amplifiers, the auxiliary sense amplifiers being equal in number to the main sense amplifiers and each producing an error signal in response to an erroneous information bit read from the main memory array through any of the main sense amplifiers, and an error correction circuit intervening between the main and auxiliary sense amplifiers and transparent to an error-free information bit read from the main memory array, the error correction circuit being responsive to the error signal from any of the auxiliary sense amplifiers for inverting the logic state of an erroneous information bit read from the main memory array.