Patent US 4,876,642

Method and apparatus for prefetching and buffering instructions between a code store and a processing element's decode logic. The apparatus is a code buffer that consists of a code RAM and its supporting logic that implements rules for bringing instructions into the code RAM from the code store and outputting them to the decode logic. These rules determine when writing to the code RAM is blocked and reading from the code RAM is blocked by using the write and read addresses and loop information stored in the supporting logic. The rules guarantee that the instructions to be executed are not overwritten, instructions being executed have, in fact, been brought into the code RAM, and loops are kept in the code RAM until they have been exited. The code buffer handles two types of branch instructions, inside branches to instructions that are within the code RAM and outside branches to instructions in the code store. Outside branches cause the branch address and status information to be sent to the code store and the code RAM and its surrounding logic to be reset. The purpose of the code buffer is to reduce the amount of time the decode logic spends waiting for instructions by providing buffering and taking advantage of the reexecution of instructions in loops.