Patent US 4,876,644

A processor adapted for parallel and/or pipelined interconnection with other like processors. An arithmetic logic unit has associated with it an output FIFO register stack having output data lines capable of parallel connection with the output data lines of other such processors, such output stack being loadable with a predetermined neutral value such that when the neutral value is present at their output data lines it permits the data present at the output lines of another such processor connected in parallel therewith to control the output data bus. The invention eliminates the need to have control over several such processors connected in parallel and/or pipelined configuration by way of external arbitration logic.