TEST PIN ASSEMBLY FOR CIRCUIT BOARD TESTER

Apparatus for testing the electrical integrity of printed circuit boards under test (BUTs), each BUT having a plurality of downwardly directed accessible nodes, the apparatus including support means for removably supporting the BUT, test circuitry including a plurality of upwardly directed channel nodes below the support means, connection means for electrically connecting the channel nodes to the BUT nodes, the connection means including a universal board carrying probes in a universal grid pattern, means to activate selective probes, and a translator board to make electrical connection between upper and lower conductors in different patterns.