CELLULAR ARRAY PROCESSOR WITH INDIVIDUAL CELL-LEVEL DATA-DEPENDENT CELL CONTROL AND MULTIPORT INPUT MEMORY

In an array of processing cells arranged as a single instruction multiple data processor, each processing cell contains logic which enables the cell to determine individually whether it will perform an arithmetic or logic operation or be in an idle condition. This cell-level logic includes a control register whose contents determine the operating or idle condition of the cell, and also includes PUSH/POP/COMPLEMENT stack mechanisms to represent multiple complex levels of conditions, and mechanisms to load the results of a cell-level test or arithmetic instruction into the control register, providing data-dependent control at the cell level.