BIFURCATED REGISTER PRIORITY SYSTEM

A dual priority hold register enables the transfer of data to memory ports having serial priority in accordance with two stages of priority. First, all latches of a high priority sector of the register are cleared. Then, the highest priority latch of the low priority sector of the register is cleared, while the latches of the higher priority register are loaded with further data. Following clearance of the low priority latch, all latches of the higher priority register are cleared once again, followed by clearance of the next highest priority latch of the lower priority register sector while the higher priority register is loaded once again. The sequence is repeated until both the higher and lower priority sectors of the register are clear.