Patent №
US 5,087,953
Granted
1992-02-11
Filed 1990
Owner
UNISYS CORPORATION, BLUE BELL, PA A CORP. OF DE
Lab
—
AI components
2
ml · hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
07593440
A method and technique for inserting additive logic into the architecture of a gate array chip package whereby spare input and output pins can later be used to alter the logic functions by either disabling or enabling certain logic units internal to the chip by external signal injection.
AI classification
AI hardware0.95
Machine learning0.93
Natural language0.00
Speech0.00
Evolutionary computation0.00
Vision0.00
Knowledge representation0.00
Planning0.00
Ownership
UNISYS CORPORATION, BLUE BELL, PA A CORP. OF DE
assignment · 54720719
Assignors
WHITTAKER, BRUCE E., BARAJAS, SAUL
On an employer assignment, the assignors are typically the inventors.
From the same owner
MULTIPROCESSOR MULTIFUNCTION ARBITRATION SYSTEM WITH TWO LEVELS OF BUS ACCESS INCLUDING PRIORITY AND NORMAL REQUESTSUS 5,146,596 · 1992METHOD OF PROVIDING FLEXIBILITY AND ALTERABILITY IN VLSI GATE ARRAY CHIPSUS 5,087,839 · 1992DIGITAL SIGNAL TRANSLATOR HAVING COMPENSATION FOR P-CHANNEL AND N- CHANNEL THRESHOLD VOLTAGE SHIFTSUS 4,942,398 · 1990BIFURCATED REGISTER PRIORITY SYSTEMUS 4,926,313 · 1990