FULLY STATIC CMOS CASCODE VOLTAGE SWITCH LOGIC SYSTEMS

A static, single-ended cascode voltage switch logic system arranged in a tree with multiple levels. Each level of each branch of the tree is comprised of a complementary pair. The invention is preferrably implemented in CMOS, so that each complementary pair consists of a p-type and an n-type transistor, the p-type FET connected at its source to a high voltage reference and at its drain to the drain of the n-type FET. The source of the n-type FET is connected to the common drain connections of the next lower-level complementary pair, or to a low voltage reference. The approach eliminates the need for passive loads, clocked loads or complementary signals, since each node is actively held high or low.