OUTPUT CIRCUIT FOR PRODUCING POSITIVE AND NEGATIVE PULSES AT A SINGLE OUTPUT TERMINAL

An output circuit provides both a positive and negative pulse output at a single output terminal in response to the receipt of a single trigger input pulse for triggering either negative-edge sensitive or positive-edge sensitive input stages of succeeding circuit elements. The circuit includes a latch responsive to the input trigger signal, and the output of the latch is coupled to the data input terminal of a first clocked flip-flop for setting the flip-flop upon receipt of the clock signal. The output of the first clocked fip-flop is coupled to the reset terminal of the latch to reset the output of the first clocked flip-flop to its initial state upon receipt of a second clock signal. The output circuit further includes a divide-by-2 flip-flop clocked by the opposite phase of the clock signal to provide a divided clock signal. A transmission gate selectively enabled by the output of the first flip-flop serves to electrically couple the divided clock signal through the transmission gate to an output terminal thereof for one cycle of the clock following receipt of the trigger pulse. At the end of one complete clock cycle following receipt of the initial trigger pulse, the transmission gate is disabled and assumes a high impedance state. A pull-up resistor or pull-down resistor may be coupled to the output terminal of the transmission gate to generate either a negative-going output pulse or a positive-going output pulse, respectively, to meet the needs of succeeding logic circuitry.