PLURAL INCOMPATIBLE INSTRUCTION FORMAT DECODE METHOD AND APPARATUS

Architectural design of processor apparatus and its method of operation permit normally incompatible plural format process instructions for dissimilar processors to be placed intermixed in the instruction storage of a single machine but to be accurately decoded and executed properly regardless. Instructions in different formats which are normally incompatible which may have been written for different machine types are placed in predefined or segregated areas of the instruction store. Instructions are fetched and decoded by the processor for execution in a manner which uses portions of both the fetched-from address in the instruction store and the instruction itself. Decoding is thus determined in part by where in the instruction store the instruction resided when fetched, and the specific instruction itself. This approach is compatible with both ordinary processor architecture and with pipelined processor architectures.