Patent US 5,146,608

A parallel computer system includes a parallel processing array for connection to a control processor to form a parallel computer. The processing array includes a plurality of processing elements that perform processing operations to process data and generate messages, each including an address, in response to commands from a control processor, and that generate status information reflecting the status of their processing operations. A communications network transfers the messages among the processors in accordance with the address information. A control processor generates commands for transmission to the processing elements in parallel to control the processing operations by the processing elements in response to the condition of composite processing status information to facilitate selection of commands to be transmitted to the processing elements. A command and status information distribution network connected to the control processor and the processing elements couples the commands generated by the control processor to the processing elements in parallel to control processing by the processing elements in parallel, and receiving status information from the processing elements in parallel and generating in response composite processing status information to control the control processor.