MASSIVELY PARALLEL DIGITAL IMAGE DATA PROCESSOR USING PIXEL-MAPPED INPUT/OUTPUT AND RELATIVE INDEXED ADDRESSING

A massively parallel digital image data processor provides a large number of processing elements arranged in a two-dimensional matrix form. Relative indexed addressing among the processing elements is provided, whereby image data may be easily accessed by and shared among all processing elements. A single-instruction/multiple-data (SIMD) architecture provides instructions to the processing elements in parallel in accordance with specific application programs therefor. The processing elements use triple-ported register files for their internal memory which may input and output data independently and simultaneously. The processing elements are memory-mapped into the address space of the processor's embedded computer to simplify addressing thereof. All image data is inputted and outputted in pixel format. All image data is transferred, stored and processed in bit-serial format.