PIPELINE FOR REMOVING AND CONCURRENTLY EXECUTING TWO OR MORE BRANCH INSTRUCTIONS IN SYNCHRONIZATION WITH OTHER INSTRUCTIONS EXECUTING IN THE EXECUTION UNIT

The parallelism of a multi-pipelined digital computer is enhanced by detection of branch instructions from the execution pipelines and concurrent processing of up to two of the detected instructions in parallel with the operations of the execution pipelines. Certain branch instructions, when detected, are removed altogether from the pipeline, but still processed. The processing is synchronized with the execution pipeline to, first, predict an outcome for detected branch instructions, second, test the conditions for branch instructions at their proper place in the execution sequence to determine whether the predicted outcome was correct, and third, fetch a corrected target instruction if the prediction proves wrong.