Patent US 5,317,705

Patent №

US 5,317,705

Granted

Owner

Lab

AI components

1

hardware

Assignment

None on record

Dataset

AIPD

2023_r1 edition

Application

08112174

A system for reducing purging of a translation lookaside buffer (TLB) to reduce operating system overhead in a system running multiple levels of virtual machines. A system typically must purge TLB entries whenever an underlying page table entry is invalidated due to paging activity on the host machine, or an underlying guest machine. A system for reducing the number of cases in which guest translations are based on host page table entries is provided. Additional logic is supplied to analyze each invalidate page table entry (IPTE) instruction to minimize the extent of purging required as a result of that instruction. When the region relocate facility is in operation, or when no pageable TLB's have been constructed, only the entry corresponding to the page table entry to be invalidated need be purged. This limited purging reduces the overhead by reducing the time spent in purging and the time required in address translation to rebuild the TLB. This time saving results in increased performance in systems with multi-level guests.

AI hardwareG06F 12/1036G06F 2009/45583G06F 2212/1016G06F 2212/683

AI classification

AI hardware0.94
Evolutionary computation0.03
Knowledge representation0.01
Natural language0.01
Planning0.00
Speech0.00
Machine learning0.00
Vision0.00
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