Patent US 5,325,367

A memory device that contains a static RAM memory is provided with data input and data output registers, an address register, and a control register for storing various control signals. The RAM has three principal modes: PA1 a. in a normal mode, all registers are accessible externally so that the memory may fulfill its standard function, PA1 b. in a scan-state, all the cited register constitute a synchronous shift register that may be serially written with a test pattern and serially read with a result pattern; in this way the memory may be subjected to a test according to the scan test principle, PA1 c. in a self test state the communication with the outer world is shut off, the address register counts through successive addresses, the memory is cycled through read-modify or read-modify-read operations, and the data read is conversed to a signature pattern for subsequent scan-out. In this way a quasi stand-alone test facility is realized. Various additional features may be implemented.