METHOD AND APPARATUS FOR SELECTIVELY COMPACTING TEST RESPONSES

Patent №

US 8,108,743

Granted

2012-01-31

Filed 2010

Owner

MENTOR GRAPHICS CORPORATION

Lab

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

12891498

A method and apparatus to compact test responses containing unknown values or multiple fault effects in a deterministic test environment. The proposed selective compactor employs a linear compactor with selection circuitry for selectively passing test responses to the compactor. In one embodiment, gating logic is controlled by a control register, a decoder, and flag registers. This circuitry, in conjunction with any conventional parallel test-response compaction scheme, allows control circuitry to selectively enable serial outputs of desired scan chains to be fed into a parallel compactor at a particular clock rate. A first flag register determines whether all, or only some, scan chain outputs are enabled and fed through the compactor. A second flag register determines if the scan chain selected by the selector register is enabled and all other scan chains are disabled, or the selected scan chain is disabled and all other scan chains are enabled. Other embodiments allow selective masking of a variable number of scan chain outputs.

AI classification

AI hardware0.61
Evolutionary computation0.10
Machine learning0.02
Vision0.01
Knowledge representation0.00
Natural language0.00
Planning0.00
Speech0.00

Ownership

MENTOR GRAPHICS CORPORATION

assignment · 257140238

Assignors

RAJSKI, JANUSZ, KASSAB, MARK, MUKHERJEE, NILANJAN, TYSZER, JERZY

On an employer assignment, the assignors are typically the inventors.

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