Patent US 5,363,496

A microprocessor incorporating a cache memory with a selective purge operation includes a control register for storing control information including page information for controlling a purge operation for purging a predetermined page divided in the cache memory, a setting portion for transferring the control information to the control register; a comparator for comparing a target page address indicated by the control information stored in the control register with an address stored in the cache memory; and an issue portion for providing a purge command to indicate the start of execution of the purge operation to the comparator based on the control information stored in the control register only when the target page address agrees with an address in the cache memory.