METHOD AND APPARATUS FOR PERFORMING DIFFERENT CACHE REPLACEMENT ALGORITHMS FOR FLUSH AND NON-FLUSH OPERATIONS IN RESPONSE TO A CACHE FLUSH CONTROL BIT REGISTER

A method and apparatus for efficiently performing a cache operation in a processor (70) for both flushing and non-flushing. One embodiment uses a cache flush control bit (100) in a data cache (90) to determine whether or not to ignore valid bits (130) during a pseudo least recently used (LRU) replacement algorithm. When the replacement algorithm is being used for flushing the data cache (90), the valid bits (130) are not used in order to make the algorithm more efficient. If the valid bits (130) are ignored, then the least recently used bits (120) are used to select the cache line that will be replaced. However, when the replacement algorithm is being used for a non-flushing replacement purpose, the valid bits (130) are used first, followed by the plurality of least recently used bits (120), to select the cache line that will be replaced.