TEST PLAN GENERATION FOR ANALOG INTEGRATED CIRCUITS

A method of generating a test plan for a circuit designed with blocks of analog, digital, or mixed signal components. Each block is treated as a separate functional unit, with a test having block inputs that are set to predetermined values. A matrix of circuit equations is set up to determine what circuit inputs will result in these block inputs. The required number of equations is obtained by identifying any circuit inputs that need to be set heuristically.