TEST BENCH GENERATOR FOR INTEGRATED CIRCUITS, PARTICULARLY MEMORIES

A computer based test bench generator (1) for verifying integrated circuits specified by models in a Hardware Description Language includes a repository (10) storing a general set of self-checking tests applicable to the integrated circuits. A capability is provided for entering behavior data (21) of an integrated circuit model (20), and for entering configuration data (22) of the integrated circuit model. The generator automatically generates test benches (30) in the Hardware Description Language by making a selection and setup of suitable tests from the repository according to the specified integrated circuit model, configuration and behavior data.