SYSTEM AND METHOF FOR MINIMIZING CACHE INTERRUPTIONS BY INHIBITING SNOOP CYCLES IF ACCESS IS TO AN EXCLUSIVE PAGE

A memory property tagging apparatus is interfaced with one or more caches which are associated with one or more microprocessors of a multiprocessor system having shared memory and a bus network. The apparatus masks off any snoop cycles on the bus network if data corresponding to an address is exclusive to its associated microprocessor(s). The apparatus can specify to its associated one or more caches whether data is cacheable or not. The apparatus can specify to its associated one or more caches whether data is to be treated as write-through or write-back. Finally, the apparatus can translate preselected memory addresses on the bus network into input/output (IO) addresses.